The present invention relates generally to integrated circuits and in particular the present invention relates to integrated differential input buffer circuits.
A differential buffer circuit is typically provided to monitor the transitions of an input signal relative to a reference signal and produce an output signal indicating the detection of a transition in the input signal.
Referring to the drawings, FIG. 1 shows a differential buffer circuit generally designated by the numeral 1 which includes complementary p-channel and n-channel transistors 7 and 9 form one inverter circuit branch 30 of the differential circuit, while complementary transistors 13 and 15 forming another inverter circuit branch 32 which is connected in parallel with branch 30 at connection nodes 29 and 31. The gates of complementary transistors 7 and 9 are connected in common to a reference voltage VREF. The gates of complementary transistors 15 and 13 are connected in common to an input voltage Vin at node 27. The drain of transistor 7 is connected to the drain of transistor 9 at node 25 which is connected to a node 21 connected to bias signal line 22. Thus, the output signal of inverter branch 30 is applied to node 21 as an input signal to the gates of complementary p-channel and n-channel transistors 5 and 11. The source of transistor 7 is connected to the drain of transistor 5 and the source of transistor 15 at node 29. The source of transistor 5 is connected to a first supply voltage Vcc through an enabling p-channel transistor 8 which receives an inverse enabling signal ENi of an enabling signal EN. The drains of transistors 15 and 13 are connected together to provide an output signal Vout at node 23. The source of transistor 13 is connected to the drain of n-channel transistor 11 and the source of transistor 9 at node 31. The source of transistor 11 is connected to a second supply voltage Vss which may be ground.
When circuit 1 is in power down mode and an enable signal EN (not shown) is in a low state, the inverse of EN, namely ENi, is in a high state, transistor 8 is off, and Vcc is not supplied to the differential buffer circuit 1. During this time the internal bias node 21 can be at ground voltage. Since the voltage on this node controls the bias power supplied to the buffer circuit 1 by controlling transistors 5 and 11, the circuit buffer 1 is slow to operate after being enabled if the first applied data signal at Vin is low. This is because a voltage cannot be quickly supplied to the output of the inverter circuit branch 32 formed by transistors 13 and 15. Accordingly, the buffer circuit 1 may not correctly operate at the beginning of an enabled operation.
Hence, what is needed is a differential buffer circuit which overcomes the above-noted shortcomings and produces proper operation of buffer circuit 1 when it is first enabled.
The present invention provides a differential buffer circuit which provides a sufficient operating voltage at bias node 21 when the buffer circuit is first enabled thereby ensuring proper differential buffer circuit operation at the time of enablement.
In one embodiment of the invention a transistor circuit responsive to an inverse enabling signal ENi is used to quickly bring a bias signal line to a proper operating voltage in response to the buffer circuit being enabled, and a delay circuit is used to produce a delayed version of the inverse enabling signal which is used to turn off the transistor circuit after a proper voltage is attained on the bias signal line.
In another embodiment of the invention, the delay circuit is omitted and the inverse of the enable signal ENi is passed directly to the bias signal line through a first transistor device to keep it at a predetermined initial voltage when the differential buffer circuit is disabled. When the inverse enable signal is exerted to turn on the buffer circuit, the first transistor device is tuned off. In the second embodiment, a second transistor device may also be used to prevent the bias signal line from drawing current when the buffer is disabled.
The above advantages and features of the invention will be more clearly understood from the following detailed description which is provided in connection with the accompanying drawings.